Share
Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS
Krishnendu Chakrabarty
(Author)
·
Brandon Noia
(Author)
·
Springer
· Paperback
Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS - Noia, Brandon ; Chakrabarty, Krishnendu
£ 102.84
£ 114.27
You save: £ 11.43
Choose the list to add your product or create one New List
✓ Product added successfully to the Wishlist.
Go to My WishlistsIt will be shipped from our warehouse between
Wednesday, July 10 and
Thursday, July 11.
You will receive it anywhere in United Kingdom between 1 and 3 business days after shipment.
Synopsis "Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS"
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
- 0% (0)
- 0% (0)
- 0% (0)
- 0% (0)
- 0% (0)
All books in our catalog are Original.
The book is written in English.
The binding of this edition is Paperback.
✓ Producto agregado correctamente al carro, Ir a Pagar.